DC-DC converters are commonly used to supply DC power to a variety of electronic systems and devices, such as, but not limited to relatively low voltage circuits, such as personal computers and portable digital assistants, as well as high voltage integrated circuits (e.g., automotive electronic subsystems) and the like, and are available in a variety of configurations for deriving a desired DC output voltage from a given source of DC input voltage. As a non-limiting example, the DC-DC converter may be configured as a voltage mode, buck architecture, such as that diagrammatically illustrated in FIG. 1, which is typically used in applications where the load current demand is relatively large.
In the buck mode converter architecture of FIG. 1, one or more power switches, shown as MOSFETs 10 and 20, have the (drain-source) current flow paths through coupled between a DC input voltage terminal to which a (line) input voltage Vin is applied, and a reference voltage terminal (e.g., ground (GND)). The common or phase node 15 between MOSFETs 10 and 20 is connected through an output inductor 25 to an output voltage node OUT, to which a storage capacitor 30 and the powered load/device (shown as a resistor 35) are connected. By controllably switching the power switches on and off, the upstream, or phase node, end of the output inductor is alternately connected between the DC input voltage Vin and the reference voltage (GND). This produces an alternately increasing and decreasing output current through the inductor to the output node OUT, which serves to deliver a prescribed DC output voltage to the load.
To regulate the DC output voltage, the converter also includes a voltage control loop, shown in broken lines 40. The voltage control loop includes an error amplifier 45, which is operative to compare a voltage representative of the voltage at the output node OUT with a reference voltage Vref, and to produce an error voltage in accordance with the difference between these two compared voltages. This error voltage is coupled to one input of a PWM comparator 50, a second input of which is coupled to receive a sawtooth voltage waveform. The output of PWM comparator 50 is a PWM waveform, the pulse width of which is defined in accordance with the crossings of the (threshold) level of the error voltage by the sawtooth voltage waveform.
The PWM voltage waveform output of the PWM comparator 50 is applied to driver circuits 55 and 60, which respectively control the turn on/off times of the MOSFET power switches 10 and 20. To meet the demand for substantial load current, the PWM voltage waveforms that control the on/off switching of the power switches 10 and 20 are typically mutually complementary, as in the case of driver circuits 55 and 60, so that a conductive path from one or the other of the input voltage source Vin and ground will be continuously provided through one or the other of the power switches to the output inductor. This mode of operation is customarily referred to as continuous conduction mode (CCM).
As shown in the functional block diagram of FIG. 2, the control loop transfer function for the converter of FIG. 1 includes a gain Gd(s) block 70, from which the output voltage Vout is derived, a feedback gain Gc (s) block 75 from which a correction voltage Vc is derived, and a PWM drive Hpwm (s) block 80, having a fixed gain 1/VM, that closes the loop from the feedback gain Gc (s) block 75 to the gain Gd (s) block 70. An examination of FIG. 2, in reveals that the control loop transfer function is proportional to the line input voltage Vin, as set forth in the gain Gd (s) block 70. As a consequence, it has been customary practice to provide loop compensation in the feedback gain Gc (s) block 75 in the form of the resistor-capacitor compensation network that is coupled with the error amplifier.
Unfortunately, because the parameters of such a loop compensation network are tailored for a prescribed value of the input voltage Vin, the control loop suffers degradation if the converter is powered by a substantially different value of line voltage. For example, if the loop compensation resistor-divider network is designed for an input voltage on the order of twelve volts, as a proximate median between a relatively low voltage value (e.g., on the order of six volts) and a relatively high voltage value (e.g., on the order of twenty-four volts), loop response will suffer as the input voltage is either reduced to a relatively low voltage value or increased to a relatively high voltage value.
To remedy this problem, a variety of feed-forward compensation schemes have been proposed. Although these conventional feed-forward compensation networks serve to make the loop transfer function independent of the input voltage, they do not provide a loop gain that is independent of the frequency of the PWM controller's sawtooth voltage waveform, which is not a fixed parameter, but is selected or programmed by the user (usually by way of an external trimming resistor). Instead, the instruction documentation for such controllers requires the user to perform mathematical calculations based upon a number of operational parameters, including the selected switching frequency, for defining the values of one or more additional (resistor and/or capacitor) components, which must be installed before using the controller.